In the name of God
[ Education
] [ Background ] [ Research
Interests ] [ Publications ] [ Courses
Taught ] [ Interesting Links ]
Educational
Background
EDUCATION
1989: Doctorate (Ph.D.) in Industrial Informatics from National
Institute of Applied Sciences (Institut National des
Sciences Appliquées (INSA)), Dept. of Electrical Engineering,
Toulouse,
France
Title of thesis: Acceleration of logic and functional simulation.
Totally distributed discrete event simulation.
1985: Master of Science (Diplome d'Etudes Approfondies) in
Informatics
and Automation (informatique et automatique) Claude Bernard University,
Lyon, France
Title of thesis: Computer Aided Education
1984: Engineering Diploma (Diplome d'ingenieur = MSc &
B.Sc.) in
Electrical Engineering, National Institute of Applied Sciences (INSA),
Lyon, France
Title of thesis: A microprocessor based control system for Michelson
and Murray's interferometer.
-
Professional
Background
Feb. 2005 - present: Associate professor, Dept. of Computer
Engineering, Sharif University of Technology, Tehran, Iran
Sept. 1989 - 2005: Assistant professor, Dept. of Computer
Engineering, Sharif University of Technology
Feb. 2002 - Oct. 2006: Director of Hardware Group, Dept. of
Computer
Engineering
2003 - 2005- Design of Automation & Robotics Lab, FPGA
Lab, and Network and Data Communication Lab.
Sept. 2000- Sept. 2003: Vice chairman for graduate studies,
Dept. of CE
Dec. 1996 - Sept. 1998: Vice chairman for graduate studies,
Dept. of CE
1994 - 1996: Head of Computing Center, Sharif University
of Technology
(this center is responsible of networking, information and internet
services, hardware equipment and software facilities)
1995: Chairman of the First Annual Computer Society of Iran
Computer
Conference (CSC 95), Sharif University of Technology, Dec. 1995
1990 - 1994: Head of Computer Engineering Department,
Sharif University
of Technology
1991: Chairman of the Microprocessor Conference
Sharif University of Technology, March 5-6, 1991
1989 - 1990: Department vice chairman for undergraduate
program,
Dept. of Computer Engineering, Sharif University of Technology.
Dec. 1985 - Nov. 1988: Lecturer, Dept. of Electrical
Engineering, National Institute of Applied Sciences (INNS), Toulouse,
France
1994 - 2005: Consultant for governmental and industrial
organizations
such as Iran Insurance Company, Alborz Insurance Company, Central
Insurance of Iran, Advanced Manufacturing Research Center,
Plan and Budget Organization.
-
Research
Interests
-
1- Wireless sensor networks
2- Performance and dependability evaluation of networks and
architectures
3- High performance &
parallel computer architectures
4- Computer arithmetic
5- Hardware/software codesign
6- Software defined radio
7- Industrial Automation
-
Publications
Journal papers:
M.
Keshtgary, A.H. Jahangir, "Survivable
network systems: Its achievements and future directions", International
Journal of Information Science and Technology, Vol
5, No 2, pp. 11-34.
A. Mahjur, A. H.
Jahangir, "Two-phase prediction of L1 data cache misses", Computers and Digital Techniques,
IEE Proceedings, Vol. 153, Issue 6, Nov. 2006, pp. 381-388.
S. Safari, A .H.
Jahangir,
H. Esmaeilzadeh, "A
Parameterized Graph-Based
Framework for High-Level Test Synthesis", Integration,
the
VLSI Journal, Elsevier, Vol. 39, Issue 4,
July 2006,
pp
363-381.
M. Keshtgary,
A. H. Jahangir, F. Al-Zahrani, A. P. Jayasumana, , "Survivability Performance Evaluation of WDM
Networks with Wavelength Converters", Photonic Network Communication Journal, Vol.11, Jan. 2006, pp. 15-27.
A. Mahjur, A. H.
Jahangir, A.
H. Gholamipour, "On the
performance of Trace Locality of Reference",
Journal of Performance
Evaluation, Elsevier,
May 2005, pp. 51-72.
S. Safari, A. H. Jahangir, H. Esmaeilzadeh, "A Novel Model for
Behavioral Test Synthesis", The CSI Journal on Computer, Oct.
2004, pp. 33-41. (in Persian)
A. H. Jahangir, "The role of Information Technology in the improvement
of knowledge and decrease of loss in Insurance Industry",
Insurance Industry Trimesterial Review, Vol. 19, No. 1, Issue 73,
Spring 2004, pp. 31-41.
Conference proceedings:
A. R. Masoum, A. H. Jahangir, Z. Taghikhani, R.
Azarderakhsh, " A New Multi Level Clustering Model to increase Lifetime
in Wireless Sensor Networks", Second International Conference on Sensor
Technologies and Applications, SENSORCOMM 2008, 25-31 Aug. 2008, pp.
185-190.
H. Habibi-Masouleh, S. A. Tahaee, A. H. Jahangir, "Finding Aggregation
Tree with Genetic Algorithm for Network Correlated Data Gathering",
Second International Conference on Sensor Technologies and
Applications, SENSORCOMM 2008, 25-31 Aug. 2008, pp. 429-434.
A. Mahjur, M. Taghizadeh A. H. Jahangir, "Lazy Instruction
Scheduling: Keeping Performance, Reducing Power", Thirteenth
International Symposium on Low Power Electronics and Design, ISLPED’08,
August 11–13, 2008, Bangalore, India, pp. 375-380.
M. Khatir, A.H. Jahangir, H. Beigy, "Investigating the Baldwin
Effect on Cartesian Genetic Programming Efficiency", IEEE Congress on
Evolutionary Computation, CEC 2008, (IEEE World Congress on
Computational Intelligence, WCCI 2008), Hong Kong, 1-6 June 2008, IEEE
Computational Intelligence Society, IEEE Press, pp. 2360-2364.
K. Mizanian, A. H. Jahangir, "A Quantitative Real-time Model for
Multihop Wireless Sensor Networks", 3rd International Conference on
Intelligent Sensors, Sensor Networks and Information, ISSNIP 2007, 3-6
Dec. 2007, pp. 79 - 84.
A. Azarfar, A.H. Jahangir,
"Voice Quality Measurement in a Typical
Router-based Network ", The 32nd
IEEE Conference on Local
Computer Networks (LCN)
, Dublin, Ireland, 15- 18 Oct. 2007.
A. Kamran, A H. Jahangir, "An
algorithm for Analysis of Analog Parts of Circuits
Described in VHDL-AMS", 5th
IEEE East-West Design & Test International Symposium, Yerevan, Armenia, 7-10 Sept. 2007, pp. 94-98.
S. A. Tahaee, A H. Jahangir, "Reducing
the Complexity of Psrtitioning Problem in High Level Synthesis", 5th
IEEE East-West Design & Test International Symposium,Yerevan, Armenia, 7-10 Sept. 2007, pp. 552-556
S.A Tahaee, A H. Jahangir, "Improving
the Performance of Partitioning with
Judicious Initial Point selection", 5th
IEEE East-West Design & Test International Symposium,Yerevan, Armenia, 7-10 Sept. 2007, pp. 563-569.
A. Mahjur, Y.
Ebrahimi, A. H.
Jahangir, "Enhancing the Performance of Direct-Mapped
Data Caches by Use Degree Prediction", Proceedings of the 14Th
Iranian Conference on Electrical Engineering, Amir Kabir
University,
Tehran, 16-18 May 2006.
A. Masum, A. H. Jahangir, "A New 3-level Clustering Model for Wireless
Sensor Network", Proceedings of the 14Th
Iranian Conference on Electrical Engineering, Amir Kabir
University,
Tehran, 16-18 May 2006. (in Persian)
R. Azarderakhsh, A. H. Jahangir and M. Keshtgary, "Network
Survivability Performance Evaluation in Wireless Sensor
Networks", 11th Intl. CSI Computer Conference, School of Computer
Science, IPM, 24-26 Jan. 2006, pp. 567-570.
A. Mahjur, A. H.
Jahangir, "Prefetching L1 Data Cache misses", 11th
Intl. CSI Computer Conference, School of Computer Science, IPM,
Poster presentation, 24-26 Jan. 2006, pp. 588-591.
R. Azarderakhsh, A. H. Jahangir and M. Keshtgary, "A New Virtual
Backbone for Wireless Ad Hoc Sensor Network with Connected Dominating
Set", Third IEEE Annual Conference on Wireless On demand Network
Systems
and Services (WONS 2006), Les Menuires, France, 18-20 Jan.
2006, pp. 191-195.
A. Mahjur, A. H. Jahangir, "Dead Block
Placement Avoidance in L1 Data Caches", 17th
IASTED International Conference on
Parallel and Distributed Systems
(PDCS 2005), Phoenix,
AZ, USA, 14-16 Nov. 2005, pp.
51-56.
M. Keshtgary, A. H. Jahangir, A. P. Jayasumana, "Network
Survivability Performance Evaluation using fault
Trees", Third IASTED Conference on Communication Computer
Networks (CCN 2005), CA, USA, Oct. 2005, pp. 158-163.
S. Safari, A. H. Jahangir, SOC Test Synthesis using Test Access
Mechanism
Design", ECTI-CON, Bangkok, Thailand, May 2005, pp. 799-803.
R. Azarderakhsh, A. H. Jahangir, Wireless sensor networks and optimized
routing algorithms for performance improvement and reduced power
consumption", 13 Th. Electrical Engineering Conference, Zanjan, Iran,
April 2005. (in Persian)
M. Keshtgary, F. Al-Zahrani, A. P. Jayasumana, A. H. Jahangir, "Network
Survivability Performance Evaluation with Applications in WDM
Networks with wavelength conversion", Proc. of 29th Annual IEEE
Conference
on Local Computer Networks (LCN 2004),
Tampa, Florida, USA, Nov. 16-18 2004, pp. 344-351.
M. Keshtgary, F. Al-Zahrani, A. H. Jahangir, A. P. Jayasumana,
"Survivability
of Multi-fiber WDM Networks with and without wavelength conversion",
Proc. of 2nd
IASTED International Conference on Communication and Computer
Networks (CCN 2004), MIT, Cambridge, MA, USA, Nov. 8-10 2004, pp.
36-41.
F. Noroozi, A. H. Jahangir, T. Kowsari, "Accelerate
Packet Classification in Linux kernel", International Conference on
Information Networking (ICOIN 2004), Pusan, Korea, Feb. 18-20,
2004.
S. Safari, H. Esmaeilzadeh, A. H. Jahangir, "Testability Improvement
during
High-Level Synthesis", 12th Asian Test Symposium (ATS), Nov. 2003,
p.505.
S. Safari, H. Esmaeilzadeh, A.H. Jahangir, "A novel
Improvement Technique for High Level Test
Synthesis", IEEE International Symposium
on Circuits and Systems (ISCAS), Bangkok, Thailand, 25-28 May 2003, pp.
V609- V612.
M. Keshtgary, A. H. Jahangir, "Survivable Network Systems: An
overview",
Fourth IEEE Information Survivability Workshop (ISW 2001/2002), March
2002, Vancouver, Canada
S. Safari, A. H. Jahangir, B. Sajad, "A novel method for behavioral
synthesis", Proc. of 7th Computer Society of Iran Annual Conference,
Dec. 2001, pp. 203-211. (in Persian)
A. H. Jahangir, H. Sarbazi-Azad, "VSCOP: An
Easy-to-collect Vector-Signal Coprocessor for", Proceedings of
the High Performance Computing Conference, HPC'ASIA, Singapore, 23-25
Sept. 1998, pp. 1151-1155.
S. Safari, H. Esmaeilzadeh, A. H. Jahangir, "A Novel Register
Allocation Method for Testability Improvements", WRTLT, Nov. 2003, pp.
96-102.
Jahangir A. H. , Saremi M. ," A real-time face recognition system
using singular value decomposition and local auto correlation
coefficients",
Proceedings of the Third Annual Computer Society of Iran Computer
Conference
(CSICC97), Iran University of Science & Technology, Tehran, Dec.
23-25,
1997 (in Persian)
Jahangir A. H. , Dehghani H., "Persian text compression",
Proceedings
of the Second Annual Computer Society of Iran Computer Conference
(CSICC96),
Amir Kabir University, Tehran, Dec. 24-26, 1996 (in Persian)
Jahangir A. H. , Dehghani H. , "Some experience in Persian text
compression",
Proceedings of the First Annual Computer Society of Iran Computer
Conference
(CSICC95), Sharif University of Technology, Tehran, Dec. 25-28, 1995
(in
Persian)
Jahangir A. H. et al, "Design and implementation of a
multiprocessor
for logic languages", Proceedings of the Third Iranian Conference on
Electrical
Engineering, Iran University of Science & Technology, Tehran, May
15-18,
1995 (in Persian, distinguished paper)
Jahangir A., Massoudi H. , Khajooe M. , "Design and
implementation
of a two-transputer-board accelerator for PC", Proceedings of the
Second
Iranian Conference on Electrical Engineering, Tarbiat Modaress
University,
Tehran, May 17-20, 1994 (in Persian)
Jahangir A. H., Sarbazi-Azad H. , "Design and implementation of a
vector coprocessor for 8088", Proceedings of the Second Iranian
Computer
Conference, Iran University of Science & Technology, Tehran, Feb.
8-10,
1994 (in Persian)
Jahangir A. H. , "Transputer, a component for high speed
processing",
Proceedings of Microprocessor Conference, Sharif University of
Technology,
Tehran, Iran, March 5-6, 1991 (in Persian)
Jahangir A. H. , Geffroy J. C. , "Totally distributed discrete
event
simulation", Proceedings of the 1989 European Simulation Conference,
Rome,
Italy, June 1989
Jahangir A. H. , Geffroy J. C. , "The use of Occam for the
validation
of distributed logic simulation", Proceedings of the 10th Occam User
Group,
IOS press, Enschede, Netherlands, April 1989.
Courses
Taught
Graduate program:
1. Advanced computer architecture
2. Computer arithmetic
3. Fault tolerant systems
4. Microprocessor II
5. Advanced microprocessors
6. DSP processor architectures
Undergraduate program:
1. Computer architecture
2. Real-time systems
3. Instrumentation and computer control (Programmable Logic
Controllers)
4. Advanced logic
5. Interface circuits
6. Scientific and technical presentation
7. Assembly programming
8. Microprocessor lab.
9. Peripheral circuits lab.
10. Network and data communication lab.
11. Logic Circuit
Supervised projects:
- More than 45 M.Sc thesis (concerning the design and
implementation
of real-time systems, hardware accelerators, parallel architecture and
programs, design of network devices, analysis and modeling of network
traffic or bandwidth...)
- More than 40 B.Sc. thesis (various topics, mainly in hardware
design)
- 3 Ph.D. theses
. Saeed Safari: High level Testable Synthesis (Fall
2005)
. Manijeh. Keshtgary: A general framework for
network survivability performance analysis (Fall 2005)
. Ali Mahjur: Prefetching L1 data cache misses (Fall
2006)
LANGUAGES
English, French, Persian
Last updated:
November 6, 2005.
