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COURSE OBJECTIVES
- How to analyze digital
logic circuits
- How to design digital
logic circuits
- Use modern CAD tools
and languages
TEXT BOOK
- "Fundamentals of Digital Logic with Verilog Design
by
Brown & Vranesic"
COURSE OUTLINES
1. Introduction
1.1. System Models
1.2. Analysis, Synthesis
& Verification of Systems
1.3. Design Process
1.4. Digital Systems
2.
Introduction to Logic Circuits
2.1. Binary-Valued Signals
2.2. Behavioral Models of
Gates: Truth Table and Logical Expressions
2.3. Boolean Algebra
2.4. Synthesis using AND,
OR and NOT Gates
2.5. Gate Networks
2.6. Analysis and Synthesis
of Logic Networks
2.7. NAND/NOR Networks
3.
An Introduction to Verilog
3.1. Verilog Uses
3.2. Verilog Modules
3.3. Behavioral vs. Structural Verilog Descriptions
3.4. Always Blocks
4.
Physical Properties of Gates
4.1. A Structural Model for Gates
4.2. MOSFET Transistors
4.3. NMOS and PMOS Logic Families
4.4. TTL Logic Families
4.5. Differences Between Real and Ideal Gates
4.6. Timing Parameters
4.7. Voltage parameters, Noise Margins and Fan-In
4.8. Current Parameters and Fan-out
4.9. Special Gate Circuits
5.
Optimized Implementation of Logic Functions
5.1. Karnaugh Map Definitions
5.2. Minimal Sum-Of-Products Expressions
5.3. Minimal Product-Of-Sums Expressions
5.4. Don’t Care Entries
5.5. Five- and Six-Variable Maps
5.6. Timing Hazards
6.
Binary Arithmetic and ALUs
6.1. Binary Arithmetic
6.2. Arithmetic Operations in Verilog
6.3. Arithmetic Circuits
7.
Combinational-circuit Building Blocks
7.1. Signal Names
7.2. Decoders
7.3. Verilog Descriptions of Decoders
7.4. Multiplexers (MUX)
7.5. Verilog Descriptions of MUX
7.6. Encoders
7.7. Verilog Descriptions of Encoders
8.
Programmable Logic Devices (Download
PDF)
8.1. Read Only Memories (ROMs)
8.2. Programmable Logic Arrays (PLAs)
8.3. Programmable Array Logics (PALs)
8.4. Complex Programmable Logic Devices (CPLDs)
8.5. Field-Programmable Gate Arrays (FPGAs)
Midterm Exam
9.
Latch and Flip-Flop
9.1. Latches & Verilog Description
9.2. Gated Latches & Verilog Description
9.3. Flip-Flops & Verilog Description
9.4. Sequential PLDS
10.
Registers and Counters
10.1. Registers
10.2. Counters
10.3. Shift-Registers
10.4. Design with MSI Components (Counters)
11. Sequential Circuit Design
11.1. State Table/Diagram
Specification
11.2. Formal Sequential Circuit
Synthesis
11.3. Transition Expressions and
Lists
11.4. Sequential Circuit Design
with Sequential PLDs
11.5. Sequential
Circuit State
Reduction
12. Sequential Circuit Analysis
12.1. Synchronous Sequential
Circuits
12.2. Synchronous Sequential
Circuit Models
12.3. Analysis Examples
12.4. Synchronous Sequential
Circuits and Verilog
13. Sequential Circuit Timing
13.1. Maximum Clock Frequency
13.2. Maximum Allowable Clock Skew
13.3. Global Setup Time, Hold Time
and Propagation Delay
13.4. Register load control
(gating the clock)
13.5. Synchronous System Structure
and Timing
14. Asynchronous Sequential Circuits (ASC)
14.1. Asynchronous Sequential
Circuits
14.2. The Fundamental Mode ASC
Model
14.3. ASC Timing Properties
14.4. A Detailed Gate Delay Model
14.5. Summary of ASC Analysis
Techniques
14.6. Outline of the ASC Synthesis
Approach
14.7. Primitive Flow Tables
14.8. State Reduction
14.9. Row Merging
14.10. State Assignment & Transition
Tables
14.11. Excitation Equations & Logic
Diagrams
14.12. Summary ASC Synthesis
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