PUBLICATIONS

Published Journal Papers

M.B. Tahoori, H. Asadi, B. Mullins, and D.R. Kaeli, "Obtaining FPGA Soft Error Rate in High Performance Information Systems," Elsevier Microelectronics Reliability, Vol. 49, Issue 5, May 2009.
H. Asadi, M.B. Tahoori, B. Mullins, D. Kaeli, and K. Granlund, “Soft Error Susceptibility Analysis of SRAM-Based FPGAs in High-Performance Information Systems,” IEEE Transactions on Nuclear Science (TNS), December 2007.
H. Asadi and M.B. Tahoori, “Analytical Techniques for Soft Error Rate Modeling and Mitigation of FPGA-Based Designs”, IEEE Transactions on Very Large Scale Integration Systems (TVLSI), December 2007.
H. Asadi, A.R. Ejlali, and S.G. Miremadi, “Fast Co-Verification of HDL Models,” Elsevier Journal of Microelectronic Engineering, Vol. 48, Issue 2, pp. 218-228, Feb. 2007.
V. Sridharan, H. Asadi, M. B. Tahoori, and D. Kaeli, “Reducing Data Cache Susceptibility to Soft Errors,” IEEE Transactions on Dependable and Secure Computing (TDSC), Nov.-Dec. 2006.

Rigorously Refereed Conference Papers (Acceptance Rate: 10% ~ 50%)

M. Fazeli, S.G. Miremadi, H. Asadi, and M.B. Tahoori, "A Fast Analytical Approach to Multi-Cycle Soft Error Rate Estimation of Sequential Circuits" 13th EuroMicro Conference on Digital System Design, Lille, France, Sept. 2010.
H. Asadi, A. Haghdoost, R. Eftekhari, "Availability Impact of Hard and Soft Failures in Enterprise Storage Systems" IEEE/IFIP Intl. Conference on Dependable Systems and Networks (DSN), Fast Abstract, Chicago, IL, June/July 2010.
H. Asadi, M. B. Tahoori, and C. Tirumurti, “Estimating Error Propagation Probabilities with Bounded Variances,” IEEE Intl. Symp. On Defect and Fault Tolerance in VLSI Systems (DFT), Rome, Italy, Sept. 2007.
B. Mullins, H. Asadi, M.B. Tahoori, D. Kaeli, K. Granlud, and R. Bauer, “Case Study: Soft Error Rate Analysis in Storage Systems”, IEEE VLSI Test Symp. (VTS07), Berkeley, CA, May 2007.
H. Asadi and M.B. Tahoori, “Soft Error Derating Computation in Sequential Circuits”, IEEE/ACM Intl. Conference on Computer Aided Design (ICCAD), San Jose, CA, November 2006.
H. Asadi and M. B. Tahoori, “Soft Error Hardening for Logic-Level Designs”, IEEE Intl. Symp. on Circuits and Systems (ISCAS), Kos, Greece, May 2006.
H. Asadi, V. Sridharan, M. B. Tahoori, and D. Kaeli, “Vulnerability Analysis of L2 Cache Elements to Single Event Upsets,” IEEE/ACM Design, Automation and Test in Europe Conference (DATE’06), Germany, March 2006.
H. Asadi, V. Sridharan, M. B. Tahoori, and D. Kaeli, “Reliability Tradeoffs in Design of Cache Memories,” Workshop on Architectural Reliability (WAR-1), held in conj. with MICRO-38, Barcelona, Spain, Nov. 2005.
H. Asadi and M. B. Tahoori, “Soft Error Modeling and Protection for Sequential Elements”, IEEE Intl. Symp. On Defect and Fault Tolerance in VLSI Systems (DFT), pp. 463-471, Monterey, CA, Oct. 2005.
G. Asadi and M. B. Tahoori, “Soft Error Mitigation for SRAM-Based FPGAs,” IEEE VLSI Test Symp. (VTS05), Palm Springs, CA, May 2005.
G. Asadi and M. B. Tahoori, “An Analytical Approach for Soft Error Rate Estimation in Digital Circuits,” IEEE Intl. Symp. on Circuits and Systems (ISCAS), pp. 2991-2994, Kobe, Japan, May 2005.
G. Asadi, V. Sridharan, M. B. Tahoori, and D. Kaeli, “Balancing Performance and Reliability in the Memory Hierarchy,” IEEE Intl. Symp. on Performance Analysis of Systems and Software (ISPASS05), Austin, Texas, March 2005.
G. Asadi and M. B. Tahoori, “An Accurate SER Estimation Method Based on Propagation Probability,” IEEE/ACM Design, Automation and Test in Europe Conference (DATE’05), March 2005.
G. Asadi and M. B. Tahoori, “Soft Error Rate Estimation and Mitigation for SRAM-Based FPGAs,” ACM Intl. Symp. on Field-Programmable Gate Arrays (FPGA-2005) , Monterey, CA, Feb. 2005.
G. Asadi, S.G. Miremadi, H.R. Zarandi, and A.R. Ejlali, “Evaluation of Fault-Tolerant Designs implemented on SRAM-Based FPGAs,” IEEE/IFIP Pacific Rim Intl. Symp. on Dependable Computing (PRDC2004), Papeete, Tahiti, March, 2004.
A.R. Ejlali, S.G. Miremadi, H.R. Zarandi, G. Asadi, and S. Sarmadi, "A Hybrid Fault Injection Approach Based on Simulation and Emulation Co-operation," IEEE/IFIP Intl. Conf. on Dependable Systems and Networks, (DSN-2003), San Francisco, June 2003.
G. Asadi, S.G. Miremadi, H.R. Zarandi, and A.R. Ejlali, "Fault Injection into SRAM-Based FPGAs for the Analysis of SEU Effects," IEEE Intl. Conference on Field programmable Technology (FPT-2003), pp. 428-430, Tokyo, Japan, December 2003.
S. Sarmadi, S.G. Miremadi, G. Asadi, and A. R. Ejlali, "Fast Prototyping with Co-Operation of Simulation and Emulation," Lecture Notes in Computer Science (LNCS), Springer-Verlag [12^thIntl. Conf. on Field Programmable Logic and Applications (FPL-2002)], Vol. 2438, M. Glesner & P. Zipf (Eds), Springer 2002.
S.G. Miremadi, S. Sarmadi, and G. Asadi, "Speedup Analysis in Simulation-Emulation Co-Operation," IEEE Intl. Conference on Field programmable Technology (FPT’02), pp. 394-398, Hong Kong, Dec 2002.

Other Publications

B. Mullins, H. Asadi, M.B. Tahoori, D. Kaeli, “Soft Error Rate Analysis in Storage Systems”, IEEE Boston Area Architecture (BARC) Workshop, Jan. 2007.
H. Asadi and M. B. Tahoori, “Timing-Logic Derating Computation Using Event Propagation Probabilities”, 2^nd Workshop on System Effects o Logic Soft Errors (SELSE 2), Urbana-Champaign, IL, April 2006.
G. Asadi and M. Hashempour, “Hardening Techniques in CMOS Combinational Logic”, IEEE 14^th North Atlantic Test Workshop (NATW05), Essex Junction, VT, May 2005.
G. Asadi, V. Sridharan, M. B. Tahoori, and D. Kaeli, “Balancing Reliability and Performance in the Memory Hierarchy,” IEEE Boston Area Architecture (BARC) Workshop, Feb. 2005.
G. Asadi and S.G. Miremadi, “Co-Verification of Partially Synthesizable Models,” IEEE 13^th North Atlantic Test Workshop (NATW04), pp. 71-78, Essex Junction, VT, May 2004.
G. Asadi and M. B. Tahoori, “An Analytical Approach for Soft Error Rate Estimation of SRAM-Based FPGAs,” MAPLD04 Conference, Washington DC, September 2004.
S. Hessabi, A. Ahmadinia, G. Asadi, S. Sarmadi, and M. Gudarzi, "Co-FFT Design: FFT Implementation on CSoC," IEEE-TTTC Intl. Conference on Automation, Quality and Testing, Robotics (AQTR-2002), pp. 312-317, Romania, May 2002.
G. Asadi, S.G. Miremadi, S. Sarmadi, and A. R. Ejlali, "Speeding up Design Verification Using Co-Operation of Simulation and Emulation," IEEE-TTTC Intl. Conf. on Automation, Quality and Testing, Robotics (AQTR-2002), Romania, 2002.

Technical Reports

H. Asadi, “Soft Error Modeling and Remediation in Digital Systems,” PhD Thesis, Department of Electrical & Computer Engineering, Northeastern University, Boston, MA.
A. Ahmadinia, S. Sarmadi, G. Asadi, "FFT Co-Design on SoC," Sharif University of Technology, Department of Computer Engineering, Sharif Univ. of Tech., Technical Report, 2001.
Asadi, "Use of Simulation-Emulation Co-operation for Speeding Up the Evaluation of VHDL-Based Digital Systems, Sharif University of Technology," Sharif Univ. of Tech., Technical Report, M.Sc. Thesis, 2002. [Farsi]
G. Asadi, "Design and Implementation of Analog Tester including Opamps, Mulivibrators and Regulators," Sharif University of Technology, Department of Computer Engineering, Technical Report, B.Sc. Thesis, 2000. [Farsi]

Memberships

· IEEE Member, 2004-Now.

· Member of Test & Reliability Group (TRG), 2004-2007, http://www.ece.neu.edu/groups/trg.

· Member of Northeastern University Computer Architecture Research Group (NUCAR), 2005-2007, http://www.ece.neu.edu/groups/nucar.

· Member of Dependable Systems Laboratory (DSL), 2001-2003, http://ce.sharif.edu/~dsl.

· Member of Sharif Rescue Robot Team, 2001-2002, http://ce.sharif.edu/~rescuerobot.

Awards

· Full Graduate Research Assistantship (GRA) award, Graduate School of Engineering., Northeastern University, Boston, MA, 2004-2007.

· Technical Award for the Best Robot Design in 2002 RescueRobocup, Fukuoka, Japan, June 2002.

· Technical Award for the Best Robot in 2001 Robot Rescue Competition Jointly organized by AAAI and RoboCup, Seattle, USA, July 2001.

· Honorary diploma from International Research Institute of Seismology and Earthquake Engineering for participating in designing and fabricating Sharif University Rescue Robot, Emdad1, 2001.

Last updated on May 1, 2010 by Hossein Asadi (حسین اسدی).

PUBLICATIONS

Published Journal Papers

M.B. Tahoori, H. Asadi, B. Mullins, and D.R. Kaeli, "Obtaining FPGA Soft Error Rate in High Performance Information Systems," Elsevier Microelectronics Reliability, Vol. 49, Issue 5, May 2009.

H. Asadi, M.B. Tahoori, B. Mullins, D. Kaeli, and K. Granlund, “Soft Error Susceptibility Analysis of SRAM-Based FPGAs in High-Performance Information Systems,” IEEE Transactions on Nuclear Science (TNS), December 2007.

H. Asadi and M.B. Tahoori, “Analytical Techniques for Soft Error Rate Modeling and Mitigation of FPGA-Based Designs”, IEEE Transactions on Very Large Scale Integration Systems (TVLSI), December 2007.

V. Sridharan, H. Asadi, M. B. Tahoori, and D. Kaeli, “Reducing Data Cache Susceptibility to Soft Errors,” IEEE Transactions on Dependable and Secure Computing (TDSC), Nov.-Dec. 2006.

Rigorously Refereed Conference Papers (Acceptance Rate: 10% ~ 50%)

M. Fazeli, S.G. Miremadi, H. Asadi, and M.B. Tahoori, "A Fast Analytical Approach to Multi-Cycle Soft Error Rate Estimation of Sequential Circuits" 13th EuroMicro Conference on Digital System Design, Lille, France, Sept. 2010.

H. Asadi, A. Haghdoost, R. Eftekhari, "Availability Impact of Hard and Soft Failures in Enterprise Storage Systems" IEEE/IFIP Intl. Conference on Dependable Systems and Networks (DSN), Fast Abstract, Chicago, IL, June/July 2010.

H. Asadi, M. B. Tahoori, and C. Tirumurti, “Estimating Error Propagation Probabilities with Bounded Variances,” IEEE Intl. Symp. On Defect and Fault Tolerance in VLSI Systems (DFT), Rome, Italy, Sept. 2007.

B. Mullins, H. Asadi, M.B. Tahoori, D. Kaeli, K. Granlud, and R. Bauer, “Case Study: Soft Error Rate Analysis in Storage Systems”, IEEE VLSI Test Symp. (VTS07), Berkeley, CA, May 2007.

H. Asadi and M.B. Tahoori, “Soft Error Derating Computation in Sequential Circuits”, IEEE/ACM Intl. Conference on Computer Aided Design (ICCAD), San Jose, CA, November 2006.

H. Asadi and M. B. Tahoori, “Soft Error Hardening for Logic-Level Designs”, IEEE Intl. Symp. on Circuits and Systems (ISCAS), Kos, Greece, May 2006.

H. Asadi, V. Sridharan, M. B. Tahoori, and D. Kaeli, “Vulnerability Analysis of L2 Cache Elements to Single Event Upsets,” IEEE/ACM Design, Automation and Test in Europe Conference (DATE’06), Germany, March 2006.

H. Asadi, V. Sridharan, M. B. Tahoori, and D. Kaeli, “Reliability Tradeoffs in Design of Cache Memories,” Workshop on Architectural Reliability (WAR-1), held in conj. with MICRO-38, Barcelona, Spain, Nov. 2005.

H. Asadi and M. B. Tahoori, “Soft Error Modeling and Protection for Sequential Elements”, IEEE Intl. Symp. On Defect and Fault Tolerance in VLSI Systems (DFT), pp. 463-471, Monterey, CA, Oct. 2005.

G. Asadi and M. B. Tahoori, “Soft Error Mitigation for SRAM-Based FPGAs,” IEEE VLSI Test Symp. (VTS05), Palm Springs, CA, May 2005.

G. Asadi and M. B. Tahoori, “An Analytical Approach for Soft Error Rate Estimation in Digital Circuits,” IEEE Intl. Symp. on Circuits and Systems (ISCAS), pp. 2991-2994, Kobe, Japan, May 2005.

G. Asadi, V. Sridharan, M. B. Tahoori, and D. Kaeli, “Balancing Performance and Reliability in the Memory Hierarchy,” IEEE Intl. Symp. on Performance Analysis of Systems and Software (ISPASS05), Austin, Texas, March 2005.

G. Asadi and M. B. Tahoori, “Soft Error Rate Estimation and Mitigation for SRAM-Based FPGAs,” ACM Intl. Symp. on Field-Programmable Gate Arrays (FPGA-2005) , Monterey, CA, Feb. 2005.

A.R. Ejlali, S.G. Miremadi, H.R. Zarandi, G. Asadi, and S. Sarmadi, "A Hybrid Fault Injection Approach Based on Simulation and Emulation Co-operation," IEEE/IFIP Intl. Conf. on Dependable Systems and Networks, (DSN-2003), San Francisco, June 2003.

G. Asadi, S.G. Miremadi, H.R. Zarandi, and A.R. Ejlali, "Fault Injection into SRAM-Based FPGAs for the Analysis of SEU Effects," IEEE Intl. Conference on Field programmable Technology (FPT-2003), pp. 428-430, Tokyo, Japan, December 2003.

S.G. Miremadi, S. Sarmadi, and G. Asadi, "Speedup Analysis in Simulation-Emulation Co-Operation," IEEE Intl. Conference on Field programmable Technology (FPT’02), pp. 394-398, Hong Kong, Dec 2002.

Other Publications

B. Mullins, H. Asadi, M.B. Tahoori, D. Kaeli, “Soft Error Rate Analysis in Storage Systems”, IEEE Boston Area Architecture (BARC) Workshop, Jan. 2007.

H. Asadi and M. B. Tahoori, “Timing-Logic Derating Computation Using Event Propagation Probabilities”, 2^nd Workshop on System Effects o Logic Soft Errors (SELSE 2), Urbana-Champaign, IL, April 2006.

G. Asadi and M. Hashempour, “Hardening Techniques in CMOS Combinational Logic”, IEEE 14^th North Atlantic Test Workshop (NATW05), Essex Junction, VT, May 2005.

G. Asadi, V. Sridharan, M. B. Tahoori, and D. Kaeli, “Balancing Reliability and Performance in the Memory Hierarchy,” IEEE Boston Area Architecture (BARC) Workshop, Feb. 2005.

G. Asadi and S.G. Miremadi, “Co-Verification of Partially Synthesizable Models,” IEEE 13^th North Atlantic Test Workshop (NATW04), pp. 71-78, Essex Junction, VT, May 2004.

G. Asadi, S.G. Miremadi, S. Sarmadi, and A. R. Ejlali, "Speeding up Design Verification Using Co-Operation of Simulation and Emulation," IEEE-TTTC Intl. Conf. on Automation, Quality and Testing, Robotics (AQTR-2002), Romania, 2002.

Technical Reports

Memberships

Awards

PUBLICATIONS

Published Journal Papers

M.B. Tahoori, H. Asadi, B. Mullins, and D.R. Kaeli, "Obtaining FPGA Soft Error Rate in High Performance Information Systems," Elsevier Microelectronics Reliability, Vol. 49, Issue 5, May 2009.

H. Asadi, M.B. Tahoori, B. Mullins, D. Kaeli, and K. Granlund, “Soft Error Susceptibility Analysis of SRAM-Based FPGAs in High-Performance Information Systems,” IEEE Transactions on Nuclear Science (TNS), December 2007.

H. Asadi and M.B. Tahoori, “Analytical Techniques for Soft Error Rate Modeling and Mitigation of FPGA-Based Designs”, IEEE Transactions on Very Large Scale Integration Systems (TVLSI), December 2007.

V. Sridharan, H. Asadi, M. B. Tahoori, and D. Kaeli, “Reducing Data Cache Susceptibility to Soft Errors,” IEEE Transactions on Dependable and Secure Computing (TDSC), Nov.-Dec. 2006.

Rigorously Refereed Conference Papers (Acceptance Rate: 10% ~ 50%)

M. Fazeli, S.G. Miremadi, H. Asadi, and M.B. Tahoori, "A Fast Analytical Approach to Multi-Cycle Soft Error Rate Estimation of Sequential Circuits" 13th EuroMicro Conference on Digital System Design, Lille, France, Sept. 2010.

H. Asadi, A. Haghdoost, R. Eftekhari, "Availability Impact of Hard and Soft Failures in Enterprise Storage Systems" IEEE/IFIP Intl. Conference on Dependable Systems and Networks (DSN), Fast Abstract, Chicago, IL, June/July 2010.

H. Asadi, M. B. Tahoori, and C. Tirumurti, “Estimating Error Propagation Probabilities with Bounded Variances,” IEEE Intl. Symp. On Defect and Fault Tolerance in VLSI Systems (DFT), Rome, Italy, Sept. 2007.

B. Mullins, H. Asadi, M.B. Tahoori, D. Kaeli, K. Granlud, and R. Bauer, “Case Study: Soft Error Rate Analysis in Storage Systems”, IEEE VLSI Test Symp. (VTS07), Berkeley, CA, May 2007.

H. Asadi and M.B. Tahoori, “Soft Error Derating Computation in Sequential Circuits”, IEEE/ACM Intl. Conference on Computer Aided Design (ICCAD), San Jose, CA, November 2006.

H. Asadi and M. B. Tahoori, “Soft Error Hardening for Logic-Level Designs”, IEEE Intl. Symp. on Circuits and Systems (ISCAS), Kos, Greece, May 2006.

H. Asadi, V. Sridharan, M. B. Tahoori, and D. Kaeli, “Vulnerability Analysis of L2 Cache Elements to Single Event Upsets,” IEEE/ACM Design, Automation and Test in Europe Conference (DATE’06), Germany, March 2006.

H. Asadi, V. Sridharan, M. B. Tahoori, and D. Kaeli, “Reliability Tradeoffs in Design of Cache Memories,” Workshop on Architectural Reliability (WAR-1), held in conj. with MICRO-38, Barcelona, Spain, Nov. 2005.

H. Asadi and M. B. Tahoori, “Soft Error Modeling and Protection for Sequential Elements”, IEEE Intl. Symp. On Defect and Fault Tolerance in VLSI Systems (DFT), pp. 463-471, Monterey, CA, Oct. 2005.

G. Asadi and M. B. Tahoori, “Soft Error Mitigation for SRAM-Based FPGAs,” IEEE VLSI Test Symp. (VTS05), Palm Springs, CA, May 2005.

G. Asadi and M. B. Tahoori, “An Analytical Approach for Soft Error Rate Estimation in Digital Circuits,” IEEE Intl. Symp. on Circuits and Systems (ISCAS), pp. 2991-2994, Kobe, Japan, May 2005.

G. Asadi, V. Sridharan, M. B. Tahoori, and D. Kaeli, “Balancing Performance and Reliability in the Memory Hierarchy,” IEEE Intl. Symp. on Performance Analysis of Systems and Software (ISPASS05), Austin, Texas, March 2005.

G. Asadi and M. B. Tahoori, “Soft Error Rate Estimation and Mitigation for SRAM-Based FPGAs,” ACM Intl. Symp. on Field-Programmable Gate Arrays (FPGA-2005) , Monterey, CA, Feb. 2005.

A.R. Ejlali, S.G. Miremadi, H.R. Zarandi, G. Asadi, and S. Sarmadi, "A Hybrid Fault Injection Approach Based on Simulation and Emulation Co-operation," IEEE/IFIP Intl. Conf. on Dependable Systems and Networks, (DSN-2003), San Francisco, June 2003.

G. Asadi, S.G. Miremadi, H.R. Zarandi, and A.R. Ejlali, "Fault Injection into SRAM-Based FPGAs for the Analysis of SEU Effects," IEEE Intl. Conference on Field programmable Technology (FPT-2003), pp. 428-430, Tokyo, Japan, December 2003.

S.G. Miremadi, S. Sarmadi, and G. Asadi, "Speedup Analysis in Simulation-Emulation Co-Operation," IEEE Intl. Conference on Field programmable Technology (FPT’02), pp. 394-398, Hong Kong, Dec 2002.

Other Publications

B. Mullins, H. Asadi, M.B. Tahoori, D. Kaeli, “Soft Error Rate Analysis in Storage Systems”, IEEE Boston Area Architecture (BARC) Workshop, Jan. 2007.

H. Asadi and M. B. Tahoori, “Timing-Logic Derating Computation Using Event Propagation Probabilities”, 2nd Workshop on System Effects o Logic Soft Errors (SELSE 2), Urbana-Champaign, IL, April 2006.

G. Asadi and M. Hashempour, “Hardening Techniques in CMOS Combinational Logic”, IEEE 14th North Atlantic Test Workshop (NATW05), Essex Junction, VT, May 2005.

G. Asadi, V. Sridharan, M. B. Tahoori, and D. Kaeli, “Balancing Reliability and Performance in the Memory Hierarchy,” IEEE Boston Area Architecture (BARC) Workshop, Feb. 2005.

G. Asadi and S.G. Miremadi, “Co-Verification of Partially Synthesizable Models,” IEEE 13th North Atlantic Test Workshop (NATW04), pp. 71-78, Essex Junction, VT, May 2004.

G. Asadi, S.G. Miremadi, S. Sarmadi, and A. R. Ejlali, "Speeding up Design Verification Using Co-Operation of Simulation and Emulation," IEEE-TTTC Intl. Conf. on Automation, Quality and Testing, Robotics (AQTR-2002), Romania, 2002.

Technical Reports

Memberships

Awards

H. Asadi and M. B. Tahoori, “Timing-Logic Derating Computation Using Event Propagation Probabilities”, 2^nd Workshop on System Effects o Logic Soft Errors (SELSE 2), Urbana-Champaign, IL, April 2006.

G. Asadi and M. Hashempour, “Hardening Techniques in CMOS Combinational Logic”, IEEE 14^th North Atlantic Test Workshop (NATW05), Essex Junction, VT, May 2005.

G. Asadi and S.G. Miremadi, “Co-Verification of Partially Synthesizable Models,” IEEE 13^th North Atlantic Test Workshop (NATW04), pp. 71-78, Essex Junction, VT, May 2004.